IEEE/IEC 61523-4-2015
IEEE/IEC International Standard - Design and Verification of Low-Power Integrated Circuits
| Fecha edición: |
2015-03-24
En Vigor
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| Idiomas disponibles: | Inglés |
| Keywords: | corruption semantics|IEEE 1801|interface specification|IP reuse|isolation|level shifting|power-aware design|power domains|power intent|power modes|power states|progressive design refinement|retention|retention strategies|IEC 61523-4 |
| Scope: | Adoption Standard - Active. A method is provided for specifying power intent for an electronic design, for use in verification of the structure and behavior of the design in the context of a given power management architecture, and for driving implementation of that power management architecture. The method supports incremental refinement of power intent specifications required for IP-based design flows. |
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