IEEE/IEC 62530-2011
IEEE/IEC International Standard - SystemVerilog -- Unified Hardware Design, Specification, and Verification Language
| Fecha edición: |
2011-05-19
En Vigor
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| Idiomas disponibles: | Inglés |
| Keywords: | assertions|design automation|design verification|hardware description language|HDL|HDVL|PLI|programming language interface|SystemVerilog|Verilog|VPI |
| Scope: | Adoption Standard - Active. This standard represents a merger of two previous standards: IEEE Std 1364-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document. |
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Otras Relaciones |
Relaciona con IEEE 1497-2001 |










