IEEE 1800-2023
IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language
| Fecha edición: |
2024-02-28
En Vigor
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| Idiomas disponibles: | Inglés |
| Keywords: | assertions|design automation|design verification|hardware description language|HDL|HDVL|IEEE Std 1800™|PLI|programming language interface|SystemVerilog|Verilog®|VPI |
| Scope: | Revision Standard - Active. The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level abstraction levels, and for writing test benches using coverage, assertions, object-oriented programming, and constrained random verification. The standard also provides application programming interfaces (APIs) to foreign programming languages. (The PDF of this standard is available at no cost at https://ieeexplore.ieee.org/browse/standards/get-program/page compliments of Accellera Systems Initiative) |
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